I'm a software engineer at Arista Networks, in Santa Clara, CA. I work on drivers for the network ASIC's in Arista's switches, especially ternary content-addressable memory (TCAM) access-control list (ACL) features, e.g. firewalls, rate-limiting, and redirection.
I'm interested in everything: operating systems, computer graphics, machine learning, compilers, music, and more! I try to create or learn something every day.
Arista Networks, Software Engineer - May 2018...Present
- User-space Broadcom ASIC drivers for TCAM ACL features.
- Ported CPU firewall to Jericho2 (400G) chip.
- Added best-effort resource allocation for BGP Flowspec.
- Fixed performance regressions in BGP Flowspec.
- Python, C++, GDB, perf, Linux, Networking
Mentor Graphics, Software Intern - May 2017...Aug 2017
- Printed circuit board (PCB) design file importer bug fixes.
- Implemented concave polygon intersection.
- Identified unsynchronized multithreaded std::vector mutation.
- Fixed stack overrun from switching thread library.
- C++, GDB, Windows, Linux, Computer Graphics
Seagate Technology, Software Intern - May 2016...Aug 2016
- Added tool to auto-generate latency heatmap for read/write.
- Python, Matplotlib, Data Visualization
University of Colorado at Boulder, B.S. Computer Science
GPA 3.887, Graduated May 2018